The present invention relates to power supply circuits and PWM circuits.
Mobile equipment such as mobile telephones have become popular in recent years, and there are an increasing number of occasions in which circuits in the equipment are loads are driven by batteries. In such cases, lower power consumption at the power supply circuit is desirable. It may also be desirable for power supply circuits to be able to respond to load changes at high speeds.
As the electronic equipment that uses integrated circuits has become popular, stable DC power supplies with low voltage and low power consumption are required.
If transistors are switched on and off in synchronism with changes in the loads and inputs to stabilize the power supply, waste power consumption can be reduced. Therefore, the efficiency of the power supply can be substantially improved. In other words, the power supply can be stabilized by changing on-periods (or on-duty) of the transistors. Synchronous rectification type switching regulators using CMOS integrated circuits are known as such efficient power supply circuits.
CMOS integrated circuits are formed by combining two kinds of MOS transistors, i.e., an N-channel transistor (hereafter simply referred to as an “NMOS”) and a P-channel transistor (hereafter simply referred to as a “PMOS”). Because of their low power consumption characteristic, they has become the mainstream of LSI technology.
FIG. 7 shows a structure of a synchronous rectification type switching regulator using a CMOS integrated circuit.
Referring to FIG. 7, a power supply circuit is composed of a synchronous rectification type switching regulator circuit that includes a PMOS on a high side (hereafter referred to as an “upper transistor”) (QP1) and an NMOS on a low side (hereafter referred to as a “lower transistor”) (QN1), which are alternately turned on and off to output a DC voltage VOUT, an error amplifier 40 that compares the output voltage of the C switching regulator circuit with a reference voltage value of a reference voltage source E to obtain an error signal, and a PWM circuit 20 that controls outputs of the switching regulator circuit to be constant by controlling the pulse width of a PWM signal based on the error signal.
The switching regulator circuit has the upper transistor (QP1) and the lower transistor (QN1) serially connected to each other with their drains D being shared between a terminal 1 that is provided with a DC voltage VIN (=a power supply voltage VDD, which is, for example, 4V) as an input voltage and a terminal 2 that is given a reference potential VSS (=a ground potential GND, which is, for example, 0V). A source S of the upper transistor (QP1) connects to the terminal 1, and a source of the lower transistor (QN1) connects to the terminal 2.
High frequency pulses SH and SL, which are obtained by inverting a PWM signal from the PWM circuit 20 by output buffers BA1 and BA2, respectively, are supplied to gates of the upper transistor (QP1) and the lower transistor (QN1), respectively. The transistors are alternately turned on and off by the high frequency pulses SH and SL to thereby generate an AC voltage VMA at an intermediate node K that is a connection point of the two transistors.
A rectification coil L1 and a stabilizing capacitor CO are serially connected between the node K and a terminal 3 that provides the reference voltage VSS; and a DC voltage VOUT that is smoothed out by the stabilizing capacitor CO is outputted from an output terminal 4 that is connected to the serially connected point. Then, the output voltage VOUT is returned to a minus (−) terminal of the error amplifier 40 through a feed back line, and compared with the reference voltage value of the reference voltage source E that is connected to a terminal 5 that gives the reference potential VSS. An error output Vb which is a comparison result given by the error amplifier 40 is supplied to the PWM circuit 20, and the pulse width of the PWM signal generated by the PWM circuit 20 is controlled by the error output. By this feed back control, the output voltage VOUT (for example, 1.5V) to be supplied to a load (not shown) is always controlled to be constant.
Conventionally, the PWM circuit 20 is composed of, for example, a comparator COMP as shown in FIG. 8. The error output Vb (see FIG. 9(a)) of the error amplifier 40 is inputted in a minus (−) terminal of the comparator COMP as a reference signal, and a triangular waveform signal Vsaw (see FIG. 9(a)) that is generated by a triangular waveform generation circuit not shown is inputted in a plus (+) terminal of the comparator COMP. As a result of the comparison, a PWM signal (see FIG. 9(b)) whose pulse width changes according to the error output Vb is outputted. The PWM signal is supplied to the upper transistor (QP1) and the lower transistor (QN1) shown in FIG. 7 as gate pulses SH and SL, respectively. However, the gate pulse SL that is supplied to the lower transistor (QN1) is formed to have a pulse width slightly narrower than that of the gate pulse SH supplied to the upper transistor (QP1) such that a through current does not flow from the power supply voltage VIN side to the reference potential VSS side if the PMOS and NMOS simultaneously turn on.
However, when the PWM circuit is formed from a comparator, and the frequency of the triangular waveform signal is set to a high frequency of, for example, about 1 MHz to have the CMOS converter circuit switch at high speeds, it is difficult to generate a PWM signal according to the high frequency and it is difficult to achieve higher speeds.
In view of the above, it has been conceived that the PWM circuit 20 may generate a PWM signal having a pulse width according to an error output Vb through creating a triangular waveform signal having a slope according to the error output Vb from a reference clock of a predetermined frequency (for example, 1 MHz), and supplying the triangular waveform signal to a potential judging circuit such as a Schmitt trigger circuit.
The PWM circuit 20 is composed as shown in FIG. 10, for example. As shown, the PWM circuit 20 includes a clock input terminal 21 that is supplied with a reference clock CLK of, for example, 1 MHz (see FIG. 11(a)); a power supply input terminal 22 that is supplied with an input voltage VIN as a power supply voltage; an input terminal 23 in which an error output Vb from the error amplifier 40 is inputted; a reference potential input terminal 24 that is given a reference potential VSS; a voltage-current converter circuit having an error amplifier 201, a reference resistance R and a current control PMOS (QP2) wherein the error output Vb is inputted in a minus (−) terminal of the error amplifier 201, a plus (+) terminal of the error amplifier 201 is connected to a serial connection point between a drain of the PMOS (QP2) and the reference resistance R, an output terminal of the error amplifier 201 is connected to a gate of the PMOS (QP2), a source of the PMOS (QP2) is connected to the power supply input terminal 22, and one end of the reference resistance R is connected to the reference potential input terminal 24; a charge-discharge circuit having a current supply PMOS (QP3), a charge capacitor C and a discharge NMOS (QN2) wherein a source of the PMOS (QP3) is connected to the power supply input terminal 22 and its drain is connected through the capacitor C to the reference potential input terminal 24, source and drain of the NMOS (QN2) are connected in parallel to both ends of the capacitor C, a gate of the PMOS (QP3) is connected to a gate of the PMOS (QP2) and an output terminal of the error amplifier 201, a gate of the NMOS (QN2) is connected to the clock input terminal 21, and the NMOS (QN2) is periodically turned on by the reference clock CLK that is supplied to its gate to discharge a stored charge of the capacitor C to thereby output a triangular waveform signal W-CLK; and a Schmitt trigger circuit 202 that receives an input of the triangular waveform signal W-CLK (see FIG. 11(b)) obtained at the output terminal of the capacitor C and generates a rectangular waveform signal (i.e., PWM signal, indicated in FIG. 11(c)) with a predetermined threshold value VTH. The PMOS (QP2) and PMOS (QP3) have the same size and the same shape, which are mutually mirror transistors.
With this configuration, in the voltage—current converter circuit, the error amplifier 201 operates in a manner that a voltage drop i·R created by a current i that flows in the reference resistance R becomes equal to the error voltage Vb inputted from the error amplifier 40 to thereby control the current, whereby the current i (=Vb/R) flows through the PMOS (QP2) and the resistance R. As a result, a current corresponding to the error voltage Vb flows through the PMOS (QP2), and the same current also simultaneously flows through the PMOS (QP3). Accordingly, the amount of current that flows through each of the transistors PMOS (QP2) and PMOS (QP3) changes according to the value of the error voltage Vb that is inputted from the error amplifier 40, and as a result, the voltage charged in the capacitor C also changes according to the value of the error voltage Vb. For example, as the error voltage Vb rises, the current value that is charged in the capacitor C linearly increases, and therefore wave height values of the triangular waveform signal that is created by charging and discharging at a constant clock cycle correspond to the increase in the voltage Vb. As a result, the slope of the triangular waveform signal that is generated at both ends of the capacitor C changes as indicated by a waveform in solid line {circle around (1)}, and waveforms in broken lines {circle around (2)} and {circle around (3)} in FIG. 11(b). By this, the pulse width of the PWM signal that is cut by the threshold value VTH at the Schmitt trigger circuit 202 becomes greater as indicated by a waveform in solid line {circle around (1)}, and waveforms in broken lines {circle around (2)} and {circle around (3)} in FIG. 11(c). In other words, the slope of the triangular waveform signal changes and the pulse width of the PWM signal is controlled according to the error voltage Vb.
According to the PWM circuit shown in FIG. 10, by the use of a Schmitt trigger circuit having an excellent response, high speed PWM controls that comply with changes in the error output Vb can be realized, and its response can be improved.